{"id":183286,"date":"2011-06-16T20:20:00","date_gmt":"2011-06-16T18:20:00","guid":{"rendered":"https:\/\/cms.galaxiemedia.fr\/tomshardware\/2011\/06\/16\/les-evolutions-du-x86-chez-intel-avec-avx2\/"},"modified":"2023-06-22T18:37:20","modified_gmt":"2023-06-22T16:37:20","slug":"les-evolutions-du-x86-chez-intel-avec-avx2","status":"publish","type":"post","link":"https:\/\/www.tomshardware.fr\/les-evolutions-du-x86-chez-intel-avec-avx2\/","title":{"rendered":"Les \u00e9volutions du x86 chez Intel, avec AVX2"},"content":{"rendered":"<p><span class=\"imgContent imgRight\"><span class=\"iZoom\"><img alt=\"Image 1 : Les \u00e9volutions du x86 chez Intel, avec AVX2\" decoding=\"async\" width=\"200\" height=\"132\" src=\"https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2012\/11\/intel-logo-200x132.jpg\" class=\"attachment-purch-200 size-purch-200\" alt=\"\" \/><\/span><\/span><\/p>\n<\/p>\n<p>Apr\u00e8s MMX, SSE (2, 3, 4, etc.) et AVX, voici <strong>AVX2<\/strong>. Cette extension du jeu d&#8217;instructions x86 sera propos\u00e9e sur une prochaine g\u00e9n\u00e9ration de processeurs, Haswell. Dans les nouveaut\u00e9s, notons un \u00ab retour aux sources \u00bb : des instructions SIMD \u2014 une seule instruction peut modifier plusieurs donn\u00e9es \u2014 capables de travailler sur les entiers en 256 bits. Retour aux sources, car le premier jeu d&#8217;instructions SIMD en x86 \u00e9tait le MMX, qui permettait justement ce type de manipulation, alors que les suivants se focalisaient essentiellement sur les donn\u00e9es en virgule flottante.<\/p>\n<\/p>\n<p>On trouve aussi des instructions qui travaillent sur des manipulations de bits, ce qui est utile en cryptographie, surtout quand on n&#8217;utilise pas AES, qui dispose d\u00e9j\u00e0 de ses instructions d\u00e9di\u00e9es. Le plus int\u00e9ressant est l&#8217;apparition du FMA (Fused Multiply-Add), une technique qui permet d&#8217;effectuer une multiplication et une addition en une seule instruction, du type A = A x B + C. C&#8217;est AMD qui devrait int\u00e9grer le premier ce type d&#8217;instructions, avec une technique diff\u00e9rente de celle d&#8217;Intel, mais c&#8217;est s\u00fbrement l&#8217;impl\u00e9mentation Intel qui sera la plus utilis\u00e9e, comme c&#8217;est le cas habituellement.<\/p>\n<\/p>\n<p>Reste le probl\u00e8me classique des jeux d&#8217;instructions de ce type : la prise en charge dans le monde r\u00e9el. En effet, si les d\u00e9monstrations montrent des gains parfois \u00e9normes, les \u00ab vrais \u00bb logiciels sont rarement optimis\u00e9s pour les jeux d&#8217;instructions r\u00e9cents. La raison est simple : le parc install\u00e9 est g\u00e9n\u00e9ralement faible et les d\u00e9veloppeurs utilisent les instructions qui sont disponibles sur la majorit\u00e9 des processeurs. Ce qui explique qu&#8217;actuellement la majorit\u00e9 des logiciels sont \u2014 au mieux \u2014 optimis\u00e9s pour les instructions SSE2, pr\u00e9sentes dans la majorit\u00e9 des processeurs du march\u00e9 (Atom compris). Bien \u00e9videmment, rien n&#8217;emp\u00eache les d\u00e9veloppeurs d&#8217;int\u00e9grer d&#8217;autres jeux d&#8217;instructions en d\u00e9tectant le type de CPU, mais \u00e7a n\u00e9cessite g\u00e9n\u00e9ralement du travail suppl\u00e9mentaire \u00e9tant donn\u00e9 qu&#8217;il faut coder plusieurs versions des algorithmes \u00e0 optimiser.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Apr\u00e8s MMX, SSE (2, 3, 4, etc.) et AVX, voici AVX2. Cette extension du jeu d'instructions x86 sera propos\u00e9e sur la prochaine g\u00e9n\u00e9ration de processeurs, Ivy Bridge.<\/p>","protected":false},"author":36,"featured_media":50650,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"ep_exclude_from_search":false,"footnotes":""},"categories":[487,4109,4107,4068,4071],"tags":[493],"hubs":[],"acf":{"post_show_excerpt":false,"post_source":{"title":"Intel","url":"http:\/\/software.intel.com\/en-us\/blogs\/2011\/06\/13\/haswell-new-instruction-descriptions-now-available\/","target":""}},"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v21.5 (Yoast SEO v22.5) - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Les \u00e9volutions du x86 chez Intel, avec AVX2<\/title>\n<meta name=\"description\" content=\"Apr\u00e8s MMX, SSE (2, 3, 4, etc.) et AVX, voici AVX2. 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