{"id":633215,"date":"2021-06-11T15:48:44","date_gmt":"2021-06-11T13:48:44","guid":{"rendered":"https:\/\/www.tomshardware.fr\/?p=633215"},"modified":"2023-06-22T17:13:48","modified_gmt":"2023-06-22T15:13:48","slug":"amd-donne-des-details-supplementaires-sur-sa-technologie-3d-chiplet","status":"publish","type":"post","link":"https:\/\/www.tomshardware.fr\/amd-donne-des-details-supplementaires-sur-sa-technologie-3d-chiplet\/","title":{"rendered":"AMD donne des d\u00e9tails suppl\u00e9mentaires sur sa technologie 3D Chiplet"},"content":{"rendered":"\n

Au Computex, Lisa Su, PDG d\u2019AMD, a pr\u00e9sent\u00e9 un surprenant Ryzen 5000 arm\u00e9 d\u2019un cache 3D vertical<\/a>. Gr\u00e2ce \u00e0 une technologie appel\u00e9e 3D Chiplet, un processeur Ryzen serait capable d\u2019embarquer jusqu\u2019\u00e0 192 Mo de cache L3. Cela augmenterait ses performances d\u2019environ 15 % dans les jeux. Dans une vid\u00e9o publi\u00e9e sur YouTube, AMD a donn\u00e9 des d\u00e9tails suppl\u00e9mentaires.<\/p>\n\n\n\n\n\n\n\n

En pratique, la technique consiste \u00e0 empiler verticalement des chiplets, les 3D V-Cache, comportant 64 Mo de cache SRAM, sur les CCD (Core Complex Die<\/em>). Pour cela, AMD rabote de 95 % la hauteur du die principal, ne laissant que 20 microm\u00e8tres de silicium ; l\u2019espace lib\u00e9r\u00e9 permet de placer la m\u00e9moire L3. Celle-ci communique avec le CCD par TSV (Through Silicon Vias<\/em>).<\/p>\n\n\n\n

AMD officialise ses cartes graphiques Radeon PRO W6000 : jusqu\u2019\u00e0 32 Go de VRAM et 60 UE<\/a><\/strong><\/p>\n\n\n\n

Des puces produites \u00e0 partir de la fin d\u2019ann\u00e9e<\/h2>\n\n\n\n

AMD avait mis en avant sa collaboration avec TSMC lors du Computex ; Effectivement, cette conception s\u2019appuie sur le proc\u00e9d\u00e9 SoIC du fondeur. TSMC d\u00e9crit SoIC<\/a> comme “un pilier technologique cl\u00e9 pour faire avancer le domaine de l’int\u00e9gration de chiplets h\u00e9t\u00e9rog\u00e8nes avec une taille r\u00e9duite et des performances accrues. Il se caract\u00e9rise par un empilement vertical \u00e0 ultra-haute densit\u00e9 pour des performances \u00e9lev\u00e9es, une faible consommation et une faible RLC (r\u00e9sistance-inductance-capacit\u00e9). Le SoIC int\u00e8gre des puces actives et passives dans un nouveau syst\u00e8me SoC int\u00e9gr\u00e9, qui est \u00e9lectriquement identique au SoC natif, pour obtenir un meilleur facteur de forme et de meilleures performances.”<\/em><\/p>\n\n\n\n

\"Image<\/a><\/figure><\/div>\n\n\n\n

Ce cache 3D vertical n\u2019aurait pas d\u2019incidence significative sur la latence ou la consommation ; il ne n\u00e9cessiterait pas non plus d\u2019optimisations logicielles particuli\u00e8res. AMD a indiqu\u00e9 qu\u2019elle initierait la production de puces dot\u00e9es de ce cache \u00e0 partir de la fin d\u2019ann\u00e9e ; pour une g\u00e9n\u00e9ration Zen 3+ d\u00e9but 2022, les processeurs Zen 4 \u00e9tant suspect\u00e9s ne pas d\u00e9barquer pas avant fin 2022<\/a> ?<\/p>\n","protected":false},"excerpt":{"rendered":"

Des chiplets 3D V-Cache empil\u00e9s verticalement sur les CCD.<\/p>","protected":false},"author":87,"featured_media":633216,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"ep_exclude_from_search":false,"footnotes":""},"categories":[487,4071,4110],"tags":[551],"hubs":[],"acf":{"display_mode":"medium-img","post_show_excerpt":true,"post_source":"","hide_sidebar":false,"hide_advertising":false},"yoast_head":"\nAMD donne des d\u00e9tails suppl\u00e9mentaires sur sa technologie 3D Chiplet<\/title>\n<meta name=\"description\" content=\"Des chiplets 3D V-Cache empil\u00e9s verticalement sur les CCD.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.tomshardware.fr\/amd-donne-des-details-supplementaires-sur-sa-technologie-3d-chiplet\/\" \/>\n<meta property=\"og:locale\" content=\"fr_FR\" \/>\n<meta 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