{"id":734847,"date":"2022-06-30T15:55:00","date_gmt":"2022-06-30T13:55:00","guid":{"rendered":"https:\/\/www.tomshardware.fr\/?p=734847"},"modified":"2023-06-22T16:28:09","modified_gmt":"2023-06-22T14:28:09","slug":"samsung-lance-sa-production-de-puces-en-3-nm","status":"publish","type":"post","link":"https:\/\/www.tomshardware.fr\/samsung-lance-sa-production-de-puces-en-3-nm\/","title":{"rendered":"Samsung lance sa production de puces en 3 nm"},"content":{"rendered":"\n<p>Comme pr\u00e9vu, <a href=\"https:\/\/www.tomshardware.fr\/samsung-la-production-de-masse-en-3-nm-doit-debuter-des-ce-trimestre\/\">Samsung a initi\u00e9 la production de masse en 3 nm<\/a>. Ce n\u0153ud 3GAE implique des transistors <em>Gate-All-Around<\/em> (GAA). Selon la firme cor\u00e9enne, par rapport au processus 5 nm, cette technologie <em>Multi-Bridge-Channel FET<\/em> (MBCFET) r\u00e9duit de 45 % la consommation d\u2019\u00e9nergie, la surface de 16 %, am\u00e9liore les performances de 23 %.<\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-full\"><a href=\"https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main1-768x511-1.jpg\"><img alt=\"Image 1 : Samsung lance sa production de puces en 3 nm\" decoding=\"async\" width=\"768\" height=\"511\" src=\"https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main1-768x511-1.jpg\" alt=\"\" class=\"wp-image-734850\" srcset=\"https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main1-768x511-1.jpg 768w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main1-768x511-1-300x200.jpg 300w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main1-768x511-1-150x100.jpg 150w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main1-768x511-1-200x133.jpg 200w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main1-768x511-1-250x166.jpg 250w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main1-768x511-1-350x233.jpg 350w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main1-768x511-1-400x266.jpg 400w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main1-768x511-1-450x299.jpg 450w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main1-768x511-1-500x333.jpg 500w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main1-768x511-1-550x366.jpg 550w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main1-768x511-1-600x399.jpg 600w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main1-768x511-1-640x426.jpg 640w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main1-768x511-1-710x472.jpg 710w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main1-768x511-1-755x502.jpg 755w\" sizes=\"(max-width: 768px) 100vw, 768px\" \/><\/a><figcaption>Cr\u00e9dit : Samsung<\/figcaption><\/figure><\/div>\n\n\n\n<p>Samsung argue que sa technologie \u00e0 base de nanofeuilles facilite l\u2019ajustement de la largeur du canal afin d&#8217;optimiser l&#8217;utilisation de l&#8217;\u00e9nergie et les performances pour r\u00e9pondre aux diff\u00e9rents besoins des clients. \u00c0 l\u2019instar de TSMC, Samsung met en avant un \u00e9cosyst\u00e8me complet, ici baptis\u00e9 SAFE, acronyme de <em>Samsung Advanced Foundry Ecosystem<\/em>.<\/p>\n\n\n\n<p>La soci\u00e9t\u00e9 explique : &#8220;\u00c0 mesure que les n\u0153uds technologiques se r\u00e9duisent et que les besoins en mati\u00e8re de performances des puces augmentent, les concepteurs de circuits int\u00e9gr\u00e9s doivent relever le d\u00e9fi de traiter d&#8217;\u00e9normes quantit\u00e9s de donn\u00e9es pour v\u00e9rifier des produits complexes comportant davantage de fonctions et une mise \u00e0 l&#8217;\u00e9chelle plus \u00e9troite. Pour r\u00e9pondre \u00e0 ces exigences, Samsung s&#8217;efforce de fournir un environnement de conception plus stable afin de r\u00e9duire le temps n\u00e9cessaire aux processus de conception, de v\u00e9rification et de validation, tout en am\u00e9liorant la fiabilit\u00e9 des produits&#8221;. Avec l&#8217;aide des partenaires, notamment Ansys, Cadence, Siemens et Synopsys, le SAFE doit aider les clients <em>&#8220;\u00e0 perfectionner leur produit dans un d\u00e9lai r\u00e9duit&#8221;<\/em>.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">En attendant le 3 nm de deuxi\u00e8me g\u00e9n\u00e9ration<\/h2>\n\n\n\n<p>Ce 3GAE (E pour <em>early<\/em>) n\u2019est qu\u2019une premi\u00e8re \u00e9tape pour le 3 nm. Les gains \u00e9voqu\u00e9s en d\u00e9but d\u2019article valent pour ce processus. Celui de deuxi\u00e8me g\u00e9n\u00e9ration permettra de r\u00e9duire la consommation d&#8217;\u00e9nergie jusqu&#8217;\u00e0 50 %, d&#8217;am\u00e9liorer les performances de 30 % et de r\u00e9duire la surface de 35 % promet Samsung.<\/p>\n\n\n\n<p class=\"has-background\" style=\"background-color:#fafafa\"><strong><a href=\"https:\/\/www.tomshardware.fr\/tsmc-devoile-sa-feuille-de-route-jusquen-2025-cap-sur-le-2-nm\/\">TSMC d\u00e9voile sa feuille de route jusqu\u2019en 2025 : cap sur le 2 nm<\/a><\/strong><\/p>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-full\"><a href=\"https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main5-754x563-1.jpg\"><img alt=\"Image 2 : Samsung lance sa production de puces en 3 nm\" decoding=\"async\" width=\"754\" height=\"563\" src=\"https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main5-754x563-1.jpg\" alt=\"\" class=\"wp-image-734849\" srcset=\"https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main5-754x563-1.jpg 754w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main5-754x563-1-300x224.jpg 300w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main5-754x563-1-150x112.jpg 150w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main5-754x563-1-200x149.jpg 200w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main5-754x563-1-250x187.jpg 250w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main5-754x563-1-350x261.jpg 350w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main5-754x563-1-400x299.jpg 400w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main5-754x563-1-450x336.jpg 450w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main5-754x563-1-500x373.jpg 500w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main5-754x563-1-550x411.jpg 550w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main5-754x563-1-600x448.jpg 600w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main5-754x563-1-640x478.jpg 640w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/06\/3nm-chip-production-main5-754x563-1-710x530.jpg 710w\" sizes=\"(max-width: 754px) 100vw, 754px\" \/><\/a><figcaption>Cr\u00e9dit : Samsung<\/figcaption><\/figure><\/div>\n\n\n\n<h2 class=\"wp-block-heading\">D\u00e9claration<\/h2>\n\n\n\n<p>Le communiqu\u00e9 de Samsung contient plusieurs d\u00e9clarations. Pour n&#8217;en citer qu&#8217;une, Tom Beckley, vice-pr\u00e9sident senior et directeur g\u00e9n\u00e9ral du groupe Custom IC &amp; PCB chez Cadence, rapporte : <\/p>\n\n\n\n<p>&#8220;Nous f\u00e9licitons Samsung pour cette \u00e9tape importante de la mise en production du GAA 3nm. Cadence a travaill\u00e9 en \u00e9troite collaboration avec Samsung Foundry pour permettre aux clients d&#8217;obtenir une puissance, des performances et une surface optimales pour ce n\u0153ud en utilisant nos solutions num\u00e9riques, de la caract\u00e9risation des biblioth\u00e8ques \u00e0 la mise en \u0153uvre et \u00e0 la validation du flux num\u00e9rique complet, le tout pilot\u00e9 par notre technologie Cadence Cerebrus bas\u00e9e sur l&#8217;intelligence artificielle pour maximiser la productivit\u00e9. Gr\u00e2ce \u00e0 nos solutions personnalis\u00e9es, nous avons collabor\u00e9 avec Samsung pour activer et valider un flux AMS complet afin d&#8217;am\u00e9liorer la productivit\u00e9, de la conception et la simulation de circuits \u00e0 la mise en page automatis\u00e9e. Nous sommes impatients de poursuivre cette collaboration pour obtenir de nouveaux succ\u00e8s en mati\u00e8re de tape-out&#8221; (le tape-out d\u00e9signe l\u2019ultime \u00e9tape du processus de conception des circuits int\u00e9gr\u00e9s, juste avant la fabrication).<\/p>\n\n\n\n<p class=\"has-small-font-size\"><em>Source : <a href=\"https:\/\/news.samsung.com\/global\/samsung-begins-chip-production-using-3nm-process-technology-with-gaa-architecture\" target=\"_blank\" rel=\"noreferrer noopener\">Samsung<\/a><\/em><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Par rapport au 5 nm, ce n\u0153ud 3GAE r\u00e9duit la consommation de 45 %, la surface de 16 %, et am\u00e9liore les performances de 23 %.<\/p>","protected":false},"author":87,"featured_media":734850,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"ep_exclude_from_search":false,"footnotes":""},"categories":[487,4068],"tags":[514],"hubs":[],"acf":{"display_mode":"medium-img","post_show_excerpt":true,"post_show_in_home":false,"post_source":"","hide_sidebar":false,"hide_advertising":false},"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v21.5 (Yoast SEO v22.5) - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Samsung lance sa production de puces en 3 nm<\/title>\n<meta name=\"description\" content=\"Par rapport au 5 nm, ce n\u0153ud 3GAE r\u00e9duit la consommation de 45 %, la surface de 16 %, et am\u00e9liore les performances de 23 %.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" 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