{"id":753268,"date":"2022-12-14T19:45:00","date_gmt":"2022-12-14T18:45:00","guid":{"rendered":"https:\/\/www.tomshardware.fr\/?p=753268"},"modified":"2023-06-22T16:46:17","modified_gmt":"2023-06-22T14:46:17","slug":"ventana-presente-un-processeur-risc-v-a-192-coeurs-destine-aux-serveurs","status":"publish","type":"post","link":"https:\/\/www.tomshardware.fr\/ventana-presente-un-processeur-risc-v-a-192-coeurs-destine-aux-serveurs\/","title":{"rendered":"Ventana pr\u00e9sente un processeur RISC-V \u00e0 192 c\u0153urs destin\u00e9 aux serveurs"},"content":{"rendered":"\n<p>\u00c0 l\u2019occasion du RISC-V Summit, qui se d\u00e9roule \u00e0 San Jose, la startup Ventana Microsystems, sp\u00e9cialis\u00e9e dans la conception de processeurs RISC-V, a pr\u00e9sent\u00e9 le premier sous cette architecture destin\u00e9 aux serveurs, le Veyron V1. Ce n\u2019est bien s\u00fbr pas un secteur sur lequel on s\u2019attend \u00e0 voir des puces RISC-V. Jusqu\u2019\u00e0 pr\u00e9sent, cette architecture de jeu d\u2019instructions open source, sert surtout pour le march\u00e9 de l\u2019Internet des objets et autres syst\u00e8mes embarqu\u00e9s.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><a href=\"https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/risc-v.jpg\"><img alt=\"Image 1 : Ventana pr\u00e9sente un processeur RISC-V \u00e0 192 c\u0153urs destin\u00e9 aux serveurs\" decoding=\"async\" width=\"1024\" height=\"613\" src=\"https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/risc-v-1024x613.jpg\" alt=\"\" class=\"wp-image-753270\" srcset=\"https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/risc-v-1024x613.jpg 1024w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/risc-v-300x180.jpg 300w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/risc-v-150x90.jpg 150w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/risc-v-200x120.jpg 200w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/risc-v-250x150.jpg 250w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/risc-v-350x209.jpg 350w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/risc-v-400x239.jpg 400w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/risc-v-450x269.jpg 450w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/risc-v-500x299.jpg 500w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/risc-v-550x329.jpg 550w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/risc-v-600x359.jpg 600w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/risc-v-640x383.jpg 640w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/risc-v-710x425.jpg 710w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/risc-v-755x452.jpg 755w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/risc-v-1320x790.jpg 1320w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/risc-v.jpg 1900w\" sizes=\"(max-width: 1024px) 100vw, 1024px\" \/><\/a><figcaption class=\"wp-element-caption\">\u00a9 Ventana Microsystems<\/figcaption><\/figure><\/div>\n\n\n<p>\u00c0 l\u2019instar <a href=\"https:\/\/www.tomshardware.fr\/sifive-devoile-deux-nouveaux-coeurs-de-processeurs-risc-v\/\">des c\u0153urs de processeur P670 et P470 d\u00e9voil\u00e9s par SiFive<\/a> d\u00e9but novembre, cette puce Veyron V1 est \u00e9labor\u00e9e sur le processus de gravure 5 nm. Chaque cluster renferme 16 c\u0153urs, et la capacit\u00e9 totale par puce est de 192 c\u0153urs. Le cache L3 partag\u00e9 est de 48 Mo. Concernant la fr\u00e9quence, elle s\u2019\u00e9l\u00e8ve jusqu\u2019\u00e0 3,6 GHz selon Ventana Microsystems. L\u2019entreprise met \u00e9galement en avant une s\u00e9curit\u00e9 avanc\u00e9e gr\u00e2ce \u00e0 des mesures d\u2019att\u00e9nuation d\u2019attaques par canaux auxiliaires, le recours aux technologies IOMMU (<em>input\u2013output memory management unit<\/em>) et AIA (<em>advanced interrupt architecture<\/em>) et des fonctionnalit\u00e9s RAS (<em>reliability, availability and serviceability<\/em>&nbsp;; &#8220;un terme d&#8217;ing\u00e9nierie du mat\u00e9riel informatique impliquant l&#8217;ing\u00e9nierie de la fiabilit\u00e9, la haute disponibilit\u00e9 et la conception de la facilit\u00e9 d&#8217;entretien&#8221;).<\/p>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-1 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><a href=\"https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv1.png\"><img alt=\"Image 2 : Ventana pr\u00e9sente un processeur RISC-V \u00e0 192 c\u0153urs destin\u00e9 aux serveurs\" decoding=\"async\" width=\"945\" height=\"510\" src=\"https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv1.png\" alt=\"\" class=\"wp-image-753271\" srcset=\"https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv1.png 945w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv1-300x162.png 300w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv1-150x81.png 150w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv1-200x108.png 200w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv1-250x135.png 250w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv1-350x189.png 350w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv1-400x216.png 400w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv1-450x243.png 450w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv1-500x270.png 500w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv1-550x297.png 550w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv1-600x324.png 600w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv1-640x345.png 640w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv1-710x383.png 710w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv1-755x407.png 755w\" sizes=\"(max-width: 945px) 100vw, 945px\" \/><\/a><figcaption class=\"wp-element-caption\">\u00a9 Ventana Microsystems<\/figcaption><\/figure><\/div><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\"><div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><a href=\"https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv2.png\"><img alt=\"Image 3 : Ventana pr\u00e9sente un processeur RISC-V \u00e0 192 c\u0153urs destin\u00e9 aux serveurs\" decoding=\"async\" width=\"941\" height=\"535\" src=\"https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv2.png\" alt=\"\" class=\"wp-image-753272\" srcset=\"https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv2.png 941w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv2-300x171.png 300w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv2-150x85.png 150w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv2-200x114.png 200w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv2-250x142.png 250w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv2-350x199.png 350w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv2-400x227.png 400w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv2-450x256.png 450w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv2-500x284.png 500w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv2-550x313.png 550w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv2-600x341.png 600w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv2-640x364.png 640w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv2-710x404.png 710w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv2-755x429.png 755w\" sizes=\"(max-width: 941px) 100vw, 941px\" \/><\/a><figcaption class=\"wp-element-caption\">\u00a9 Ventana Microsystems<\/figcaption><\/figure><\/div><\/div>\n<\/div>\n\n\n\n<p class=\"has-background\" style=\"background-color:#fafafa\"><strong><a href=\"https:\/\/www.tomshardware.fr\/pour-son-hpsc-la-nasa-a-choisi-des-coeurs-cpu-risc-v-sifive\/\">Pour son HPSC, la NASA a choisi des c\u0153urs CPU RISC-V SiFive<\/a><\/strong><\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Bient\u00f4t une bataille \u00e0 4 ?<\/h2>\n\n\n\n<p>Par ailleurs, la conception g\u00e9n\u00e9rale de la puce est assez classique : une interface de donn\u00e9es D2D sur un c\u00f4t\u00e9, de la m\u00e9moire DDR5 sur deux autres et du PCIe Gen5 sur le dernier. L&#8217;interface Die-to-Die (D2D) est compatible <em>Harness of Wire<\/em> (HoW) et <em>Universal Chiplet Interconnect Express<\/em> (UCIe), des protocoles \u00e9galement pris en charge par Intel, AMD, NVIDIA ou Arm.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><a href=\"https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv3.png\"><img alt=\"Image 4 : Ventana pr\u00e9sente un processeur RISC-V \u00e0 192 c\u0153urs destin\u00e9 aux serveurs\" decoding=\"async\" width=\"550\" height=\"517\" src=\"https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv3.png\" alt=\"\" class=\"wp-image-753269\" srcset=\"https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv3.png 550w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv3-300x282.png 300w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv3-150x141.png 150w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv3-200x188.png 200w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv3-250x235.png 250w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv3-350x329.png 350w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv3-400x376.png 400w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv3-450x423.png 450w, https:\/\/www.tomshardware.fr\/content\/uploads\/sites\/3\/2022\/12\/veyronv3-500x470.png 500w\" sizes=\"(max-width: 550px) 100vw, 550px\" \/><\/a><figcaption class=\"wp-element-caption\">\u00a9 Ventana Microsystems<\/figcaption><\/figure><\/div>\n\n\n<p>Comme indiqu\u00e9 en d\u00e9but d\u2019article, pour le moment, l&#8217;architecture RISC-V est principalement utilis\u00e9e sur le march\u00e9 de l\u2019informatique embarqu\u00e9e. Plusieurs raisons \u00e0 cela : sa capacit\u00e9 \u00e0 offrir une utilisation efficace de l&#8217;\u00e9nergie, sa viabilit\u00e9 \u00e0 long terme, ou simplement le fait que l\u2019architecture soit ouverte et libre. L\u2019avenir nous dira si le Veyron V1 parvient \u00e0 se faire une place au sein des serveurs, terrain de jeu des processeurs x86 Xeon d\u2019Intel et EPYC d\u2019AMD, <a href=\"https:\/\/www.tomshardware.fr\/30-de-pc-arm-dici-2026\/\">sur lequel commence toutefois \u00e0 l\u00e9g\u00e8rement empi\u00e9ter les puces Arm<\/a>.<\/p>\n\n\n\n<p>Ventana Microsystems sugg\u00e8re que sa V1 peut servir \u00e0 de nombreuses t\u00e2ches, des h\u00e9bergeurs web aux centres de donn\u00e9es consacr\u00e9s aux services de streaming.<\/p>\n\n\n\n<p class=\"has-small-font-size\"><em>Source : <a href=\"https:\/\/news.mydrivers.com\/1\/879\/879104.htm\" target=\"_blank\" rel=\"noreferrer noopener\">Mydrivers<\/a><\/em><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Avec cette puce, con\u00e7ue en 5 nm, la soci\u00e9t\u00e9 ambitionne de concurrencer les processeurs x86 Intel Xeon et AMD EPYC sur un secteur ou m\u00eame Arm a du mal \u00e0 le faire, celui des serveurs.<\/p>","protected":false},"author":87,"featured_media":753270,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"ep_exclude_from_search":false,"footnotes":""},"categories":[487,4071],"tags":[],"hubs":[],"acf":{"display_mode":"medium-img","post_show_excerpt":true,"post_show_in_home":true,"post_source":"","hide_sidebar":false,"hide_advertising":false},"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v21.5 (Yoast SEO v22.5) - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Ventana pr\u00e9sente un processeur RISC-V \u00e0 192 c\u0153urs destin\u00e9 aux serveurs<\/title>\n<meta name=\"description\" content=\"Avec cette puce, con\u00e7ue en 5 nm, la soci\u00e9t\u00e9 ambitionne de concurrencer les processeurs x86 Intel Xeon et AMD EPYC sur un secteur ou m\u00eame Arm a du mal \u00e0 le faire, celui des serveurs.\" \/>\n<meta name=\"robots\" content=\"index, follow, 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